Responsibilities
- AI/ML & Data‑Driven Development: Design, develop, and evaluate AI/ML models to analyze large‑scale simulation, regression, and debug data (logs, waveforms, coverage, assertion failures). Build ML‑based classification, clustering, or ranking models for failure triage, anomaly detection, and root‑cause identification. Develop agentic or workflow‑driven AI solutions that integrate with existing verification and debug pipelines. Create datasets and features from RTL, simulation artifacts, firmware traces, and verification metadata.
- Tooling & Automation: Implement and enhance Python‑based automation frameworks for data extraction, preprocessing, training, and inference. Integrate AI/ML solutions with existing DV tools, simulators, and infrastructure. Prototype dashboards, reports, or visualizations to communicate model outputs and insights to engineers.
- Silicon & Verification Context: Collaborate with Design, Verification, and Firmware teams to understand controller architecture, RTL behavior, and verification methodologies like UVM. Leverage knowledge of SystemVerilog, assertions, and simulation flows to contextualize AI/ML solutions (hands‑on RTL development is not the primary responsibility). Assist in improving verification efficiency through intelligent test prioritization, coverage analysis, or debug guidance.
- Collaboration & Communication: Work multi-functionally with AI, DV, Design, and Infrastructure teams. Present results, insights, and prototypes to technical partners. Contribute to standardization and procedures for AI‑assisted silicon workflows.
Basic qualifications
- Bachelor’s or Master’s Degree in Computer Engineering, Electrical Engineering, Computer Science, or related field
- Background or coursework in Machine Learning, AI, Data Science, or Systems strongly preferred
- Prior experience or academic projects involving hardware‑software interaction or AI applied to systems.
Preferred qualifications
- AI / ML: Strong foundation in machine learning, data science, or applied AI. Experience with Python and common ML/data libraries (e.g., NumPy, pandas, scikit‑learn, PyTorch, TensorFlow). Familiarity with model evaluation, dataset creation, and feature engineering.
- Silicon / Systems (Working Knowledge): Basic to intermediate understanding of digital design concepts (RTL, finite state machines, pipelines, memory controllers). Familiarity with SystemVerilog / Verilog or SVA or UVM at a conceptual or usage level (deep DV expertise not required). Exposure to simulation, logs, waveforms, or coverage data.
- Automation & Scripting: Proficiency in Python; experience with Perl, Tcl, or shell scripting. Experience building automation pipelines or tooling in an engineering environment.
Tags & focus areas
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