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Selected role

Senior Engineer, Physical Design AI/ML

Samsung Semiconductor Inc (US) San Jose, CA, US

$138k - $206k Senior Full-time

Please Note:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World's Technology Together

Our technology solutions power the tools you use every day-including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.

*Job Title Senior Physical Design AI/ML Engineer, Logic Pathfinding Lab

What You'll Do**

We are looking for physical design engineers who have demonstrated skills in applying AI / Machine Learning tools in improving design simulation accuracy and throughput in predicting design performance, power, and area (PPA). Experience in optimization of design-technology co-optimization (DTCO) knobs in advanced logic nodes (2nm or beyond) is preferred.

The candidate will be a key technical member of the Logic Pathfinding Lab, part of the Samsung Semiconductor Inc (SSI) in San Jose. He or she will join a team of experts in researching and evaluating advanced technology options, and assisting in knowledge / technology transfer to the Samsung Logic Technology Development (TD) in Korea. The successful candidate will be responsible for researching and evaluating new device architectures, materials, and integration schemes through chip design metrics to meet the need of sub-2nm technology nodes. The candidate should have demonstrated skills and experience in standard cell architecture creation, logic cell library characterizations Place and Route, Process Design Kit (PDK) generation, and a strong understanding of Logic process integration. The candidate should have excellent communication skills, and be able to collaborate with and guide multiple organizations, including research consortia.

Location: Daily onsite presence at our San Jose office/headquarters in alignment with our Flexible Work policy

Reports to: Sr Director

Direct Reports: N/A

Design, build, and implement machine learning and generative models to optimize chip layout designs to maximize performance, power, and area (PPA) efficiency, while using explicit domain knowledge of hardware design rules and constraints
Automate and accelerate Design Implementation steps such as Floor-planning, Placement and Routing, Clock Tree Synthesis, using exploratory PDKs developed by the team
Automate and accelerate Verification steps such as Design Rule Checks (DRC) and Layout versus Schematic (LVS) Checks using exploratory PDKs developed by the team
Collaborate with other team members to automate all aspects of exploratory PDK generation, including developing automated QA systems
Applying machine learning techniques to extract and develop correlations among data in different domains, e.g. device, RO benchmark circuits, larger circuit blocks, at different operating conditions
Develop internal benchmarking capability based on available data, modeling, or learning from multiple sources, and create assessments to share with internal R&D team
Complete other responsibilities as assigned.

What You Bring

PhD with industry experience preferred
RTL synthesis, place and route, and timing analysis skills
Understanding of clock and power delivery network schemes
Hands-on experience on machine learning or deep learning projects for scientific and/or engineering applications, e.g., regression, surrogate modeling, inverse design, graph neural networks
Strong Python and/or C++ skills, including expertise in machine learning packages like PyTorch and Tensorflow
Experience in using Bayesian optimization and/or active learning frameworks for design space exploration
Expertise with agentic AI frameworks (LangGraph, CrewAI, ADK)
You're inclusive, adapting your style to the situation and diverse global norms of our people.
An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
Innovative and creative, you proactively explore new ideas and adapt quickly to change.

Preferred qualifications

Familiarity with state-of-the-art AI workloads and their compute and memory requirements
Experience with setting up and optimization of a local, private, compute cluster to run latest LLM models
Proficiency in EDA tools for synthesis and layout
Prior experience using generative AI for chip design/optimization

#LI-SF1

Equal Opportunity Employment Policy

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

Our Commitment to Innovation and Fairness

At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically.

Recruiting Agency Policy

We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.

Applicant AI Use Policy

At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified.

Trade Secret Notice

By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

Applicant Privacy Policy

https://semiconductor.samsung.com/about-us/careers/us/privacy/

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